PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 49

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-14
The figure illustrates the correlation of the PCI interface to the Local Master Interface. The table gives a clock-by-
clock description of each event in the figure.
Figure 2-14. 32-bit Master Write Transaction with Local Wait State
Table 2-18. 32-bit Master Write Transaction with Local Wait State
CLK
1
2
3
4
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_cben_in[3:0]
lm_data_xfern
lm_status[3:0]
l_ad_in[31:0]
lm_req32n
and
cben[3:0]
ad[31:0]
lm_gntn
lm_rdyn
devseln
framen
irdyn
trdyn
PCI Data
reqn
gntn
par
clk
Phase
Table 2-18
Idle
Idle
Idle
Idle
1
The lm_req32n signal is asserted on the Local Master interface by the local master to request for
32-bit data transaction. The local master issues the PCI starting address, the bus command, and
the burst length during the same clock cycle on l_ad_in, lm_cben_in and lm_burst_length,
respectively.
The Core’s Local Master Interface detects the asserted lm_req32n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
2
show master-inserted and target-inserted wait states occurring on write transactions.
Termination
Bus
3
Bus Length
Command
Don’t care
Address
( = 3 )
Bus
4
5
Don’t care
Don’t care
Address
Loading
6
Don’t care
Command
Don’t care
Enable 1
Address
Data 1
49
Byte
Bus
7
Bus Length
Address
Parity
( = 3 )
Description
Enable 1
8
Data 1
Byte
Enable 2
Data 2
Byte
Data Parity 1
Transaction
9
Bus
2
Don’t care
Enable 2
10
Data 2
Byte
Enable 3
Data 3
Byte
Data Parity 2
Functional Description
11
1
Enable 3
Data 3
Byte
PCI IP Core User’s Guide
12
Don’t care
Don’t care
Parity 3
Data
Termination
Termination
13
Normal
Bus
0
14