PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 111

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-43. 32-bit Target Burst Read Transaction with a 64-bit Local Interface
CLK
1
2
3
4
5
6
7
Turn around
PCI Data
Address
Phase
Data 1
Data 2
Wait
Wait
Wait
The master asserts framen and drives ad[31:0] and cben[3:0].
The master tri-states ad[31:0] and drives the first byte enables (Byte Enable 1) on cben[3:0].
If the master is ready to receive data, it asserts irdyn.The Core starts to decode the address and
command. It drives the lt_address_out to the back-end.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock following bar_hit.
If the back-end application is ready to put data out on the next cycle, it asserts lt_rdyn.
The Core asserts lt_ldata_xfern since lt_rdyn was asserted on the previous cycle and the
initial address is QWORD aligned. The back-end drives the first QWORD (Data 1 and Data 2) on
l_ad_in.
Quad Word Aligned
With lt_rdyn asserted for the previous two cycles, the burst cycle starts. The PCI IP core asserts
trdyn and puts Data 1 on ad[31:0].
The Core de-asserts lt_ldata_xfern. If irdyn is asserted on the previous cycle, the Core
asserts lt_hdata_xfern to the back-end. With lt_hdata_xfern de-asserted the previous
cycle, the back-end does not increment the address counter and holds the QWORD (Data 1 and
Data 2) on l_ad_in.
Double Word Aligned
With lt_rdyn asserted for the previous two cycles, the burst cycle starts, so the Core asserts
trdyn and puts Data 1 on ad since the initial address is DWORD aligned. Notice that the lower
DWORD from l_ad_in is discarded.
The Core de-asserts lt_hdata_xfern. If both irdyn and lt_rdyn are asserted on the previ-
ous cycle, the Core asserts lt_ldata_xfern to the back-end. With lt_hdata_xfern asserted
the previous cycle, the back-end can increment the address counter and put the next QWORD
(Data 2 and Data 3) on l_ad_in.
Quad Word Aligned
If the master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables. The Core keeps trdyn asserted and puts Data 2 on and loads the appropriate byte
enables.
The Core de-asserts lt_hdata_xfern. If both irdyn and lt_rdyn are asserted on the previ-
ous cycle, the Core asserts lt_ldata_xfern to the back-end. With lt_hdata_xfern asserted
the previous cycle, the back-end can increment the address counter and put the next QWORD
(Data 3 and Data 4) on l_ad_in.
Double Word Aligned
If the master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables on cben[3:0].
If the back-end keeps lt_rdyn asserted previous two cycles, the Core keeps trdyn asserted
and puts Data 2 on ad[31:0]. If the master is still ready to receive data, it keeps irdyn asserted
and drives the byte enables on cben[3:0].
The Core de-asserts lt_ldata_xfern. If irdyn is asserted on the previous cycle, the Core
asserts lt_hdata_xfern to the back-end. With lt_hdata_xfern de-asserted on the previous
cycle, the back-end does not increment the address counter and holds the QWORD (Data 2 and
Data 3) on l_ad_in.
111
Description
Functional Description
PCI IP Core User’s Guide