PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 121

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PCI-T64-O4-N2

Manufacturer Part Number
PCI-T64-O4-N2
Description
FPGA - Field Programmable Gate Array PCI Target 64B
Manufacturer
Lattice
Datasheet

Specifications of PCI-T64-O4-N2

Factory Pack Quantity
1
Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-47. Advanced Configuration Read Transactions
Advanced Configuration Space write accesses are similar to the 32-bit target write transactions with additional PCI
and Local bus signals.
CLK
1
2
3
4
5
6
7
8
Turn around
Turn around
PCI Data
Address
Phase
Data 1
Wait
Wait
Wait
Idle
Figure 2-43
The master asserts framen and idsel. It and drives the configuration address on ad[31:0]
and the read command on cben[3:0].
The master tri-states the ad[31:0] lines and drives the first byte enables cben[3:0]. If the mas-
ter is ready to receive data, it asserts irdyn.
The Core starts to decode the address and command. The target drives the lt_address_out to
the back-end.
If there is an address match, the Core drives the new_cap_hit signals to the back-end. The
back-end can use the new_cap_hit as a chip select.
If the device select timing is set to slow, the Core asserts devseln on the clock after
new_cap_hit. If the back-end is ready to put data out on the next cycle, it can assert lt_rdyn.
The Core asserts lt_data_xfern since lt_rdyn was asserted the previous cycle. The back-
end drives the first DWORD (Data 1) on l_ad_in.
With lt_rdyn asserted for the previous two cycles, the Core asserts trdyn and puts Data 1 on
ad[31:0].
The master relinquishes control of framen and cben[3:0]. It de-asserts irdyn if both trdyn
and irdyn were asserted on the last cycle.
The Core relinquishes control of ad[31:0]. It de-asserts both devseln and trdyn if both trdyn
and irdyn were asserted on the last cycle. The Core also signals to the back-end that the trans-
action is complete by clearing new_cap_hit. The Core de-asserts lt_data_xfern.
The Core relinquishes devseln and trdyn.
and
Table 2-48
illustrate advanced Configuration Space write transactions.
121
Description
Functional Description
PCI IP Core User’s Guide

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