PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 140

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Parameter Settings
Options Tab
Figure 3-3
shows the contents of the Options tab. This example shows the PCI Master/Target 33.
Figure 3-3. Options Tab
Devsel Timing
Timing of Devsel
The slowest time for a device to assert the devseln signal for all accesses except the configuration accesses. The
PCI Core supports only the slow decode setting.
Expansion ROM BAR
Expansion ROM
When selected, includes support for the Expansion ROM option.
Address Space Size
Specifies the Expansion ROM address space size.
Read Only and Read Only Address
When Read Only is selected, the Expansion ROM base address is specified by the Read Only Address parameter
and can only be read by other PCI devices. When Read Only is not selected, the Expansion ROM base address
can be specified by another PCI master device via the PCI bus.
Capabilities Pointer
The Capabilities Pointer indicates the starting location of the Capabilities List.
CardBus CIS Pointer
The CardBus CIS Pointer is 32-bit register at location 28h in the Configuration Space. For more information on set-
ting this register, refer to the CardBus specification.
Fast Back-to-Back
This option determines if the master Core supports two or more complete PCI transactions without an idle state
between them.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide