PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 135

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-57. 32-bit Target Abort for Write Transaction
CLK
4
5
6
7
8
9
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal is driven low to indicate that the back-end application is ready to receive data on the next two cycles.
The target asserts trdyn because lt_rdyn was asserted on previous cycle. The first data phase is completed.
The trdyn signal remains low because the lt_rdyn signal was driven low two clock cycles before. The
lt_data_xfern signal is asserted because the lt_rdyn signal was de-asserted in the previous cycle.
The target transfers data 1 on lt_data_out[31:0].
Because the back-end wants to abort the transaction the lt_abortn signal is driven low.
A target abort is requested as the devseln and the trdyn signals are de-asserted and the stopn signal is
asserted.
The PCI master de-asserts the framen to acknowledge the target abort.
The PCI master terminates the transaction by de-asserting the irdyn. The PCI IP core de-asserts the stopn.
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Description
Functional Description
PCI IP Core User’s Guide