PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 54

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-16
assumption that the device select timing is set to slow and wait states are not inserted. The figure illustrates how
the PCI interface correlates to the Local Master Interface. The table gives a clock-by-clock description of each
event that occurs in the figure.
Table 2-19. 32-bit Master Burst Read Transaction with a 32-bit Local Interface (Continued)
CLK
11
12
and
Turn around
Phase
Table 2-20
Idle
Since the previous data phase was completed, the Core transfers Data 3 on
l_data_out[31:0] and decreases the lm_burst_cnt to zero.
The Core relinquishes control of framen and cben. It de-asserts irdyn and changes
lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted last cycle.
The target relinquishes control of ad[31:0]. It de-asserts devseln and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 3 are available on l_data_out[31:0].
With lm_data_xfern asserted, the local master can safely read Data 3.
The Core relinquishes control of irdyn and de-asserts lm_data_xfern, and the local master
de-asserts lm_rdyn since all of the burst data have been read.
show an example of a 32-bit burst data transfer during a write transaction with the
54
Description
Functional Description
PCI IP Core User’s Guide