PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 43

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
The 64-bit memory write transaction is similar to the 32-bit write transaction with additional PCI signals required for
64-bit signaling.
Table 2-15. 32-bit Master Single Read Transaction with a 64-bit Local Interface (Continued)
CLK
11
12
Turn around
Phase
Figure 2-12
Idle
Since the previous data phase was completed, the Core transfers Data 2 on
l_data_out[63:32] and decreases the lm_burst_cnt to zero.
The Core relinquishes control of framen, req64n and cben. It de-asserts irdyn and changes
lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted last cycle.
The target relinquishes control of ad[31:0]. It de-asserts devseln and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_hdata_xfern to the local master to signify Data 2 is available on l_data_out[63:32].
With lm_hdata_xfern asserted, the local master can safely read Data 2.
The Core relinquishes control of irdyn and de-asserts lm_hdata_xfern, and the local master
de-asserts lm_rdyn since all of the burst data have been read.
and
Table 2-16
show a basic 64-bit write transaction.
43
Description
Functional Description
PCI IP Core User’s Guide