PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 156

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
LatticeECP3 FPGAs
Table A-7. Performance and Resource Utilization
Ordering Part Number
Table A-8
LatticeECP3.
Table A-8. OPN for LatticeECP3 PCI IP Core
Target 33 MHz, 32-bit
PCI/Local/Address bus width
Target 33 MHz, 64-bit
PCI/Local/Address bus width
Target 66 MHz, 32-bit
PCI/Local/Address bus width
Target 66 MHz, 64-bit
PCI/Local/Address bus width
Master/Target 33 MHz, 32-bit
PCI/Local/Address bus width
Master/Target 33 MHz, 64-bit
PCI/Local/Address bus width
Master/Target 66 MHz, 32-bit
PCI/Local/Address bus width
Master/Target 66 MHz, 64-bit
PCI/Local/Address bus width
1. Performance and utilization data are generated using an LFE3-95EA-7FN1156CES device with Lattice Diamond 1.0 software. Performance
IPexpress User-Configurable
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for
Mode
33 MHz
33 MHz
66 MHz
66 MHz
33 MHz
33 MHz
66 MHz
66 MHz
Speed
SLICEs
1005
1076
1550
483
612
589
809
683
PCI Bus
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
LUTs
1341
1059
1552
1691
2570
706
918
963
Master/Target
Master/Target
Master/Target
Master/Target
1
Target
Target
Target
Target
156
Type
Registers
470
592
491
612
640
847
661
867
PCI-MT32-E3-U6
PCI-MT64-E3-U6
PCI-MT32-E3-U6
PCI-MT64-E3-U6
PCI-T32-E3-U6
PCI-T64-E3-U6
PCI-T32-E3-U6
PCI-T64-E3-U6
sysMEM
EBRs
OPN
0
0
0
0
0
0
0
0
(PCI Interface)
Resource Utilization
External Pins
PCI IP Core User’s Guide
48
87
48
87
50
89
50
89
f
MAX
33
33
66
66
33
33
66
66