PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 68

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-20
figure shows how the PCI interface correlates to the Local Interface. The table gives a clock-by-clock description of
each event illustrated in the figure.
Figure 2-20. 32-bit Master Burst Write Transaction With a 64-bit Local Interface
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_cben_in[7:4]
lm_64bit_transn
lm_hdata_xfern
lm_ldata_xfern
l_ad_in[63:32]
lm_cben_in[3:
lm_status[3:0]
l_ad_in[31:0]
lm_req64n
and
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
lm_gntn
lm_rdyn
devseln
ack64n
framen
req64n
par64
trdyn
irdyn
reqn
gntn
par
clk
0]
Table 2-24
1
2
illustrate a burst transaction for a 32-bit PCI IP core with a 64-bit Local Interface. The
Termination
Bus
3
Bus Length
Command
Don’t care
Don’t care
Don’t care
Address
( = 2 )
Bus
4
5
Don’t care
Don’t care
Address
Loading
Don’t care
Don’t care
6
Command
Don’t care
Enable 1
Enable 2
Address
Data 1
Data 2
Byte
Byte
Bus
Don’t care
Bus Length
7
( = 2 )
68
Enable 2
Address
Parity
Byte
8
Data 2
Byte Enable 1
Data 1
Byte Enable 3
9
Data 3
4
Byte Enable 4
Transaction
Parity 1
Data 4
Data
Bus
Don’t care
10
Don’t care
Don’t care
Enable 2
Data 2
Byte
3
Don’t care
11
Enable 3
Parity 2
Data 3
Data
Byte
2
Functional Description
12
Enable 4
PCI IP Core User’s Guide
Parity 3
Data 4
Byte
Data
1
Don’t care
Don’t care
13
Don’t care
Don’t care
Parity 4
Data
Termination
Termination
14
Normal
Bus
0
15