PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 66

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-23. 32-bit Master Burst Read Transaction with a 64-Bit Local Interface
CLK
1
2
3
4
5
6
7
8
9
Turn around
Address
Phase
Data 1
Data 2
Idle
Idle
Idle
Idle
Idle
The lm_req32n signal is asserted by the local master to request 32-bit data transaction. The
local master issues the PCI starting address, the bus command, and the burst length during the
same clock cycle to l_ad_in, lm_cben_in, and lm_burst_length, respectively.
The Core’s Local Master Interface detects the asserted lm_req32n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The Core
asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the starting address, the bus command, and the burst length are
being latched.
The Core asserts framen to start transaction and the local master de-asserts lm_req32n when
the previous lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request another
PCI bus transaction.
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[3:0]. Asserting lm_rdyn also
means the local master is ready to read data. If it is not ready to read data, it keep lm_rdyn de-
asserted until it is ready.
The Core de-asserts reqn when framen was asserted but lm_req64n was de-asserted on the
previous cycle.
The target only asserts devseln to indicate it doesn’t acknowledge the 64-bit transaction.
The Core tri-states the ad[31:0] lines and drives the byte enables (Byte Enable 1). Since
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read data.
Because the master performs the burst transactions, it keeps framen asserted.
The Core de-asserts lm_64bit_transn to indicate the current data transaction is 32-bit wide. It
de-asserts lm_gntn to follow gntn.
The target asserts trdyn and puts Data 1 on ad[31:0].
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the local master is ready to read the first DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 1 on l_data_out[31:0]
and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_ldata_xfern and de-asserts lm_hdata_xfern to the local master to signify Data 1 are
available on l_data_out[31:0]. With lm_ldata_xfern asserted, the local master can safely
read Data 1 and increment the address counter.
If the local master keeps lm_rdyn asserted on the previous cycle, the Core keeps irdyn
asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next DWORD
(Data 2) on ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted. Since both
irdyn and trdyn are asserted, the second data phase is completed on this cycle.
66
Description
Functional Description
PCI IP Core User’s Guide