PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 129

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-47. 32-bit Target Disconnect Without Data for Write Transaction
Table 2-53. 32-bit Target Disconnect Without Data for Write Transaction
CLK
4
5
6
7
8
9
l_data_out[31:0]
lt_disconnectn
lt_addressout
lt_data_xfern
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
framen
lt_r_nw
lt_rdyn
stopn
Description
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal is driven low to indicate that the back-end application is ready to receive data.
The trdyn signal is driven low because the lt_rdyn signal was driven low on the previous clock cycle.
Data 1 is presented to the PCI bus via ad[31:0].
Because the target can not complete any more PCI data phases the lt_rdyn signal is driven high and
lt_disconnectn signals are driven low.
The target asserts lt_data_xfern to the back-end to signify Data 1 is available on the lt_data_out.
The trdyn signal is de-asserted since the lt_rdyn signal was driven high the previous cycle. And the stopn
signal is asserted since the lt_disconnectn signal was driven low the previous cycle.
The PCI master de-asserts the framen to acknowledge the disconnection initiated by the target.
The PCI IP core disconnects from the PCI bus by de-asserting the devseln and stopn.
Idle
irdyn
trdyn
par
clk
1
Don’t care
Command
Address
Bus
0x00
2
Address
Parity
3
Don’t care
Byte Enable 1
4
Data 1
Data Parity 1
5
129
6
0x01
Address
Data 1
Don’t care
Don’t care
7
Don’t care
8
Don’t care
9
Functional Description
PCI IP Core User’s Guide
10
0x00
11