PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 96

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-31. Basic Configuration Write
Table 2-36. Basic Configuration Write
PCI Target I/O Read and Write Transactions
Designing a PCI target application using I/O space is not recommended for several reasons. They include legacy
device conflicts, and full address and byte enable decoding for all I/O locations. However, the PCI IP core does sup-
port I/O space. Transactions to I/O locations are similar to the basic memory transactions discussed in the Basic
PCI Target Read and Write Transactions section.
CLK
1
2
3
4
5
6
7
cben[3:0]
ad[31:0]
devseln
framen
trdyn
irdyn
idsel
stopn
par
Turn around
clk
PCI Bus
Address
Phase
Data
Wait
Wait
Wait
Idle
1
Command
Address
The master asserts framen and idsel. It drives the configuration address and configuration
write command. The configuration address is ad[1:0] = 00 (type zero access); ad[7:2] =
(Configuration DWORD address); ad[10:8] = (function number); ad[31:11] = unused.
The master drives the first byte enables (Byte Enable 1). If the bridge is ready to write data, it
asserts irdyn and drives the first DWORD (Data 1) on ad[31:0]. The master signals the last
data phase when it de-asserts framen.The Core starts to decode the address and command.
The address decode continues.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln. The Core should be ready to
get the data on the next cycle.
The trdyn signal is asserted and the Core writes the DWORD. The Core also asserts stopn to
ensure the configuring transaction is single data phase.
The master relinquishes control of framen, ad[31:0] and cben[3:0]. It de-asserts irdyn if
both trdyn and irdyn were asserted last cycle.
The Core de-asserts devseln, trdyn and stopn if both trdyn and irdyn were asserted last
cycle.
The Core relinquishes control of devseln, trdyn and stopn.
Bus
2
Address
Parity
3
Enable 1
4
Data 1
Byte
96
Data Parity 1
5
Description
6
7
Functional Description
PCI IP Core User’s Guide
8
9