MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet
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MC68HC908QC16 MC68HC908QC8 MC68HC908QC4 Data Sheet M68HC08 Microcontrollers MC68HC908QC16 Rev. 5 4/2008 freescale.com ...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007, 2008. All rights reserved. ...
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... April, 2008 5.0 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Description values DD Characteristics, reverted to Rev. 3 stop I Page Number(s) N/A 237 240 243 247 24 107 237 240 246 261 107 108 112 113 123 150 234 246 values 246 DD Freescale Semiconductor ...
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... Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Chapter 16 Timer Interface Module (TIM1 .189 Chapter 17 Timer Interface Module (TIM2 .205 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .257 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 5 ...
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... List of Sections MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
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... Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.4.2 Pin Leakage Error 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 7 ...
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... COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev DDA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SSA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFL Chapter 4 Chapter 5 Computer Operating Properly (COP) Freescale Semiconductor ...
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... Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 6 Central Processor Unit (CPU) Chapter 7 External Interrupt (IRQ) Chapter 8 Keyboard Interrupt Module (KBI) 9 ...
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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.7.1 Oscillator Input Pin (OSC1 103 10.7.2 Oscillator Output Pin (OSC2 103 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Chapter 9 Low-Voltage Inhibit (LVI) Chapter 10 Oscillator Mode (OSC) Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.3.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 11 Input/Output Ports (PORTS) Chapter 12 Periodic Wakeup Module (PWU) Chapter 13 11 ...
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... Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.3.2 Clock Start-Up from POR 155 14.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Chapter 14 System Integration Module (SIM) Freescale Semiconductor ...
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... Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.3.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.3.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.3.6.2 Mode Fault Error 180 15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 15 13 ...
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... TIM1 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.3.1 TIM2 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Chapter 16 Timer Interface Module (TIM1) Chapter 17 Timer Interface Module (TIM2) Freescale Semiconductor ...
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... Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 18.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 18.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 18.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.3.1.6 Baud Rate 230 18.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 18 Development Support 15 ...
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... SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 19.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 19.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Ordering Information and Mechanical Specifications 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Chapter 19 Electrical Specifications Chapter 20 Freescale Semiconductor ...
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... See 19.11 Oscillator Characteristics 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 0.4 FLASH RAM Memory Size 16 Kbytes 512 bytes ...
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... MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 are available in these packages: – 28-pin small outline integrated circuit package (SOIC) – 28-pin thin shrink small outline package (TSSOP) – 20-pin SOIC – 20-pin TSSOP – 16-pin SOIC – 16-pin TSSOP MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
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... The MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 are available in 16-pin, 20-pin, and 28-pin packages. Figure 1-2 shows the pin assignment for these packages. 1.5 Pin Functions Table 1-2 provides a description of the pin functions. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor MCU Block Diagram 19 ...
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... Figure 1-1. Block Diagram CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
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... PTA3/RST/KBI3 14 15 28-PIN ASSIGNMENT MC68HC908QCxx SOIC NOTE: T2CH0 and T2CH1 can be repositioned using TIM2POS in CONFIG2. Figure 1-2. MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 Pin Assignments MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor V SS PTB0/SPSCK/AD4 PTB1/MOSI/T2CH1/AD5 PTA0/T1CH0/AD0/KBI0 PTA0/T1CH0/AD0/KBI0 PTB1/MOSI/T2CH1/AD5 PTA1/T1CH1/AD1/KBI1 PTB0/SPSCK/AD4 ...
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... Description Input/Outpu t Power Power Input/Output Input/Output Input Input Input/Output Input/Output Input Input Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output Input Input Input Input/Output Input/Output Input Input/Output Input/Output Input/Output Input — Continued on next page Freescale Semiconductor ...
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... T2CH0 and T2CH1 can be repositioned using TIM2POS in CONFIG2. 3. Pins not available on 16-pin devices (see note in 4. Pins not available on 16-pin or 20-pin devices (see note in MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 1-2. Pin Functions (Continued) Description 11.1 Introduction) ...
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... AD5 → MOSI → T2CH1 → PTB1 AD6 → MISO → T2CH0 (2) → PTB2 AD7 → SS → T2CLK → PTB3 AD8 → RxD → T2CH0 (2) → PTB4 (2) AD9 → TxD → T2CH1 → PTB5 T1CH2 → PTB6 T1CH3 → PTB7 PTCx PTDx Registers Freescale Semiconductor ...
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... Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 6 Central Processor Unit (CPU) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure for more information on addressing modes. Figure 2-1, ...
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... BYTES $FDFF MC68HC908QC8 Memory Map Figure 2-1. Memory Map $0040 RAM ↓ 384 BYTES $01BF $01C0 RESERVED ↓ 128 BYTES $023F $BE00 RESERVED ↓ 12,288 BYTES $EDFF $EE00 FLASH MEMORY ↓ 4096 BYTES $FDFF MC68HC908QC4 Memory Map Freescale Semiconductor ...
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... See page 109. Reset: Read: Port B Input Pullup Enable $000C Register (PTBPUE) Write: See page 111. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Bit PTA5 PTA4 0 Unaffected by reset PTB7 ...
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... AM1 R AM0 ACLK Unimplemented Bit 0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AROVFL ARD8 Reserved U = Unaffected Freescale Semiconductor ...
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... Write: See page 199. Reset: Read: TIM1 Counter Modulo $0023 Register High (T1MODH) Write: See page 200. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Bit ARD7 ARD6 ARD5 ARD4 ...
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... Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 ELS2B ELS2A TOV2 CH2MAX Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 ELS3B ELS3A TOV3 CH3MAX Reserved U = Unaffected Freescale Semiconductor ...
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... Reset: TIM2 Counter Register Read: High Write: $0241 (T2CNTH) Reset: See page 214. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Bit Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset Bit 7 Bit 6 ...
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... ELS0B ELS0A TOV0 CH0MAX Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 PWUF 0 PWUIE SMODE PWUACK PS3 PS2 PS1 PS0 Bit 3 Bit 2 Bit 1 Bit Reserved U = Unaffected Freescale Semiconductor ...
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... Write: See page 222. Reset: Read: Break Status and Control $FE0B Register (BRKSCR) Write: See page 223. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Bit POR PIN COP ILOP ...
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... BPR5 BPR4 Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 FLASH location with factory programmed trim value. LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented Bit BPR3 BPR2 BPR1 BPR0 TRIM3 TRIM2 TRIM1 TRIM0 = Reserved U = Unaffected Freescale Semiconductor 0 ...
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... RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM). LDHX #RamLast+1 TXS MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address IF22- $FFD0- ...
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... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev supply. The program and erase operations are DD NOTE ( HVEN Bit 0 MASS ERASE PGM Freescale Semiconductor ...
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... A page erase of the vector page will erase the internal oscillator trim value at $FFC0. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE NOTE FLASH Memory (FLASH) 37 ...
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... A mass erase will erase the internal oscillator trim value at $FFC0. 1. When in monitor mode, with security sequence failed (see stead of any FLASH address. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev (1) within the FLASH memory address range. NOTE NOTE CAUTION 18.3.2 Security), write to the FLASH block protect register in- Freescale Semiconductor ...
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... Memory Characteristics. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE (1) . NOTE maximum, see 19 ...
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... SET HVEN BIT 6 WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED Y 9 PROGRAMMING THIS ROW CLEAR PGM BIT WAIT FOR A TIME, t NVH CLEAR HVEN BIT WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...
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... With this mechanism, the protect start address can be $XX00, $XX40, $XX80, or $XXC0 within the FLASH memory. See Figure 2-6 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also ...
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... Start of Address of Protect Range The entire FLASH memory is protected. $C040 (1100 0000 0100 0000) $C080 (1100 0000 1000 0000) $C0C0 (1100 0000 1100 0000) $FF40 (1111 1111 0100 0000) $FF80 (1111 1111 1000 0000) The entire FLASH memory is not protected (1) Freescale Semiconductor ...
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... AN2690 — Low Frequency EEPROM Emulation on the MC68HC908QY4 An EEPROM emulation driver, available at www.freescale.com, has been developed and qualified: AN3040 — M68HC08 EEPROM Emulation Driver MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor FLASH Memory (FLASH beyond the HV 19.17 Memory Characteristics ...
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... Memory MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
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... The approximation is taken and then rounded to the nearest 10- or 8-bit value to provide greater accuracy and to provide a more robust mechanism for achieving the ideal code-transition voltage. Figure 3-2 shows a block diagram of the ADC10 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 3-1 and V as its supply and reference DD ...
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... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 47
... Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If the available clocks are too slow, the ADC10 will not perform according to specifications. If the available MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ADCLK ADCK ...
Page 48
... A write to ADSCR occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCLK occurs. • The MCU is reset. • The MCU enters stop mode with ACLK not enabled. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 49
... MHz, then the conversion time for a single 10-bit conversion is: 21 ADCK cycles Conversion time = Number of bus cycles = 11.25 µ MHz = 45 cycles The ADCK frequency must be between f maximum to meet A/D specifications. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ACLKEN 0 1 ≥ Bus ...
Page 50
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev lower than V / (4096*I AS ADVIN to V (if available). REFH REFL to V (if available). DDA SSA at a quiet point in the ground plane REFL SSA noise but will increase effective conversion time DD , one-time error. LSB ) high for less than Leak (if available). This will Freescale Semiconductor ...
Page 51
... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. • Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor – ...
Page 52
... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev sheet. Freescale Semiconductor ...
Page 53
... REFL potential There will be a brief current associated with V SSA charging. If externally available, connect the V ground location. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ) DDA as its power pin. In some packages, V DDA pin to the same voltage potential as V DDA for good results ...
Page 54
... Any write to ADSCR with ADCO set and the ADCH bits not all 1s will abort the current conversion and begin continuous conversions. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev AIEN ADCO ADCH4 ADCH3 Unimplemented 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor . SSA ...
Page 55
... If any unused or reserved channels are selected, the resulting conversion will be unknown. 2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 3-2. The successive approximation converter subsystem is turned off Table 3-2. Input Channel Select ADCH2 ...
Page 56
... Read: ADLPC ADIV1 Write: Reset: 0 Figure 3-7. ADC10 Clock Register (ADCLK) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev AD6 AD5 AD4 AD3 ADIV0 ADICLK MODE1 Bit Bit 0 0 AD9 AD8 Bit 0 AD2 AD1 AD0 Bit 0 MODE0 ADLSMP ACLKEN Freescale Semiconductor ...
Page 57
... Long sample time (23.5 cycles Short sample time (3.5 cycles) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 3-3. ADC10 Clock Divide Ratio ADIV0 Divide Ratio (ADIV) ...
Page 58
... MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion ADICLK specifies the input clock source and conversions will not continue in stop mode MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 59
... The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 4-1 Bit 7 Read: IRQPUD IRQEN Write: Reset: 0 POR Unimplemented Figure 4-1. Configuration Register 2 (CONFIG2) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE and Figure 4- TIM2POS ...
Page 60
... Figure 4-2. Configuration Register 1 (CONFIG1) COPRS — COP Reset Period Selection Bit 1 = COP reset short cycle = 8176 × BUSCLKX4 0 = COP reset long cycle = 262,128 × BUSCLKX4 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev NOTE LVIRSTD LVIPWRD LVITRIP Bit 0 SSREC STOP COPD Freescale Semiconductor ...
Page 61
... COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor for the LVI’s voltage trip points for each of the modes. DD NOTE NOTE Functional Description ...
Page 62
... Configuration Registers (CONFIG1 and CONFIG2) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 63
... COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 14 System Integration Module (SIM) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details ...
Page 64
... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 4 Configuration Registers (CONFIG1 and MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev NOTE 14.8.1 SIM Reset Status NOTE Figure 5-1. 5.4 COP Control Register) clears the COP CONFIG2). Register. Freescale Semiconductor ...
Page 65
... COP timeout period after entering or exiting stop mode. 5.8 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor LOW BYTE OF RESET VECTOR ...
Page 66
... Computer Operating Properly (COP) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 67
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 6.3 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 67 ...
Page 68
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers Unaffected by reset Figure 6-2. Accumulator ( Figure 6-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
Page 69
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 70
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev NOTE 2 1 Bit Freescale Semiconductor ...
Page 71
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 71 ...
Page 72
... SP2 9EDB IMM DIR EXT IX2 IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 73
... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...
Page 74
... SP1 9EE3 ff 4 SP2 9ED3 DIR INH INH IX1 SP1 9E6B ff rr DIR INH 4A 1 INH 5A 1 IX1 SP1 9E6A IMM DIR EXT IX2 IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
Page 75
... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
Page 76
... IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 IX1 SP1 9EE7 ff 4 SP2 9ED7 DIR EXT IX2 IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
Page 77
... Memory location N Negative bit 6.8 Opcode Map See Table 6-2. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...
Page 78
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 79
... The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor for more information on Figure 7-1 for port ...
Page 80
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 81
... The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Use the BIH or BIL instruction to read the logic level on the IRQ pin. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE V DD ...
Page 82
... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev NOTE sheet. Freescale Semiconductor ...
Page 83
... IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 84
... External Interrupt (IRQ) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 85
... TO PULLUP/ PULLDOWN ENABLE KBIP0 1 0 KBIx S KBIEx TO PULLUP/ KBIPx PULLDOWN ENABLE Figure 8-1. Keyboard Interrupt Block Diagram MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ACKK RESET V DD CLR KBI LATCH MODEK Figure 8-2 for port location of these KEYF ...
Page 86
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 87
... If the MODEK bit is clear, the keyboard interrupt inputs are edge sensitive. The KBIPx bit will determine whether an edge sensitive pin detects rising or falling edges. A KBI vector fetch or software clear immediately clears the KBI latch. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Functional Description 87 ...
Page 88
... MCU out of wait mode. 8.5.2 Stop Mode The KBI module remains active in stop mode. Clearing IMASKK in KBSCR enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev NOTE Freescale Semiconductor ...
Page 89
... Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor KBI During Break Interrupts Figure 8-2 for the port pins that 89 ...
Page 90
... KBIx pin not enabled as keyboard interrupt pin R — Reserved bit This reserved bit should always be written and will read 0. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev KEYF KBIE5 KBIE4 KBIE3 Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 91
... KBIP5–KBIP0 — Keyboard Interrupt Polarity Bits Each of these read/write bits enables the polarity of the keyboard interrupt detection Keyboard polarity is high level and/or rising edge 0 = Keyboard polarity is low level and/or falling edge MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 92
... Keyboard Interrupt Module (KBI) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 93
... LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are user selectable options found in the configuration register FROM CONFIGURATION REGISTER LOW V DD DETECTOR LVITRIP FROM CONFIGURATION REGISTER MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 4 Configuration Registers (CONFIG1 and STOP INSTRUCTION FROM CONFIGURATION REGISTER LVIRSTD LVIPWRD > TRIPR ≤ V ...
Page 94
... In the configuration register, LVIPWRD DD TRIPF rises above the rising trip point voltage greater than V by the typical hysteresis voltage, V TRIPR TRIPF NOTE operating range. The actual DD and 19.8 3.3-V DC Electrical must See Chapter 14 System TRIPR ) for the higher V TRIPF by polling DD Freescale Semiconductor HYS ...
Page 95
... Bit 7 Read: LVIOUT Write: Reset Unimplemented LVIOUT — LVI Output Bit This read-only flag becomes set when the V when V voltage rises above MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 9-2. LVI Status Register (LVISR) voltage falls below the V DD ...
Page 96
... Low-Voltage Inhibit (LVI) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev Freescale Semiconductor ...
Page 97
... The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL oscillator circuit, the RC oscillator, or the internal oscillator in stop mode. OSCENINSTOP in the configuration register can be used to override this signal. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 10-1 for information on PTAPUEN register. for port ...
Page 98
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 99
... All devices are factory programmed with a trim value that is stored in FLASH memory at location $FFC0. This trim value is not automatically loaded into OSCTRIM register. User software must copy the trim value MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 10-2 shows only the logical relation of XTALCLK to OSC1 ...
Page 100
... In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 10-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 100 10.8.1 Oscillator Status and Control Freescale Semiconductor ...
Page 101
... The OSC2EN bit can be set to enable the OSC2 output function on the pin. Enabling the OSC2 output can affect the external RC oscillator frequency, f MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE ) is included in the diagram to follow strict Pierce ...
Page 102
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 102 INTCLK 0 1 EXTERNAL RC RCCLK OSCILLATOR 1 0 OSC1 OSC2- available for alternative pin function See the Electricals section for component value. OSCOPT = EXTERNAL RC SELECTED BUSCLKX2 BUSCLKX4 2 ALTERNATIVE PIN FUNCTION OSC2EN sheet. Freescale Semiconductor ...
Page 103
... While running off the internal clock source, the user can use bits in this register to select the internal clock source frequency. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 10-1. OSC2 Pin Function OSC2 Pin Function ...
Page 104
... Internal Clock Frequency 0 4.0 MHz — default reset condition 1 8.0 MHz 0 12.8 MHz 1 25.6 MHz ECFS0 External Crystal Frequency 0 8 MHz – 32 MHz 1 1 MHz – 8 MHz 0 32 kHz – 100 kHz 1 Reserved 2 1 Bit 0 ECGST ECFS0 ECGON 10.3.2.2 Internal to External Freescale Semiconductor ...
Page 105
... Increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed oscillator period. The oscillator period is based on the oscillator frequency selected by the ICFS bits in OSCSC. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 106
... Oscillator Mode (OSC) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 106 Freescale Semiconductor ...
Page 107
... PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor (KBI)) ...
Page 108
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 108 PTA5 PTA4 Unaffected by reset KBI5 KBI4 = Reserved = Unimplemented Figure 11-1. Port A Data Register (PTA DDRA5 DDRA4 DDRA3 Unimplemented NOTE Bit 0 PTA2 PTA3 PTA1 PTA0 KBI3 KBI2 KBI1 KBI0 Chapter 8 Keyboard Interrupt Module 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...
Page 109
... Corresponding port A pin configured to have internal pull if its DDRA bit is set Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor DDRAx RESET PTAx Figure 11-3. Port A I/O Circuit ...
Page 110
... PTB5 PTB4 PTB3 Unaffected by reset Figure 11-5. Port B Data Register (PTB DDRB5 DDRB4 DDRB3 Accesses to PTA Read Write Pin PTA5–PTA0 Pin PTA5–PTA0 PTA5–PTA0 PTA5–PTA0 2 1 Bit 0 PTB2 PTB1 PTB0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor (3) (3) (5) ...
Page 111
... Corresponding port B pin configured to have internal pull if its DDRB bit is set Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit. Table 11-2 summarizes the operation of the port B pins. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 11-7. Port B I/O Circuit ...
Page 112
... Input, Hi-Z Output DDRB7–DDRB0 NOTE level on this pin in normal operation PTC3 Unaffected by reset Figure 11-9. Port C Data Register (PTC) Accesses to PTB Read Write Pin PTB7–PTB0 Pin PTB7–PTB0 PTB7–PTB0 PTB7–PTB0 2 1 Bit 0 PTC2 PTC1 PTC0 Freescale Semiconductor (3) (3) ...
Page 113
... When DDRCx reading address $0002 reads the PTCx data latch. When DDRCx reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 114
... Read/Write (2) DDRC2–DDRC0 Input (4) DDRC2–DDRC0 Input, Hi-Z Output DDRC2–DDRC0 PTD6 PTD5 PTD4 PTD3 Unaffected by reset 2 1 Bit Accesses to PTC Read Write Pin PTC3–PTC0 Pin PTC3–PTC0 PTC3–PTC0 PTC3–PTC0 2 1 Bit 0 PTD2 PTD1 PTD0 Freescale Semiconductor (3) (3) ...
Page 115
... When DDRDx reading address $0003 reads the PTDx data latch. When DDRDx reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 116
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 116 Table 11-4. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (2) DDRD7–DDRD0 Input (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 2 1 Bit Accesses to PTD Read Write (3) Pin PTD7–PTD0 (3) Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 Freescale Semiconductor ...
Page 117
... PWUIE, in PWUSC enables a PWU interrupt request. The PWUF can be cleared by writing to the PWU acknowledge bit, PWUACK in PWUSC PWU interrupt vector fetch. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor µ minutes with an adjustment resolution of better than 1% for on enabling BUSCLKX4 to run in stop mode ...
Page 118
... PWU module (PWUON = 0) before entering wait mode. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 118 PWUMOD COUNTER = PWUMOD PWUP =? PWU COUNTER CLK PRESCALER EN RST RESET PWUCLKSEL PWUACK RESET VECTOR FETCH PWUIE DECODER Freescale Semiconductor PWUF PWUIREQ ...
Page 119
... Enables or disables periodic wakeup interrupts • Enables or disables the module during stop mode Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-2. Periodic Wakeup Status and Control Register (PWUSC) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor PWUF PWUON PWUCLKSEL ...
Page 120
... These read/write bits select one of the sixteen prescaler outputs to be the input to the PWU counter. The PWUP register can only be written to when PWUON is clear. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 120 NOTE PS3 NOTE 2 1 Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...
Page 121
... The PWUMOD register can only be written to when PWUON is clear. Bit 7 Read: Bit 7 Write: Reset: 0 Figure 12-4. Periodic Wakeup Modulo Register (PWUMOD) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 12-1. Prescaler Selection PWU Counter Clock Source (PWU Clock Divided by ...
Page 122
... Periodic Wakeup Module (PWU) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 122 Freescale Semiconductor ...
Page 123
... Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 13-1 for 123 ...
Page 124
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 125
... RWU SBK WAKEUP CONTROL BUS CLOCK ENHANCED PRESCALER BUSCLKX4 ÷ -> SCI_CLK = BUSCLK -> SCI_CLK = BUSCLKX4 Figure 13-2. ESCI Module Block Diagram MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS SCTE TC SCRF OR IDLE LOOPS RECEIVE FLAG CONTROL CONTROL BKF ...
Page 126
... BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Figure 13-3. SCI Data Formats Figure 13-3. NEXT START BIT STOP BIT PARITY OR DATA NEXT BIT START BIT BIT 8 STOP BIT Freescale Semiconductor ...
Page 127
... When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed data bits and a 0 where the stop bit should be, resulting in a total consecutive 0 data bits. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor BAUD ÷ 16 ...
Page 128
... SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver interrupt request. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 128 Freescale Semiconductor ...
Page 129
... ILTY PSSB2 PSSB1 PEN PSSB0 PTY RECEIVER INTERRUPT REQUEST ERROR INTERRUPT REQUEST Figure 13-5. ESCI Receiver Block Diagram MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS SCR2 SCR1 SCR0 BAUD ÷ 16 DIVIDER DATA RxD RECOVERY ALL ZEROS M ...
Page 130
... START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 13-6. Receiver Data Sampling Table 13-1. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No LSB Noise Flag Freescale Semiconductor ...
Page 131
... Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 13-2. Data Bit Recovery Data Bit Determination ...
Page 132
... STOP DATA SAMPLES Figure 13-7. Slow Data Figure 13-7, the receiver counts 154 RT cycles at the point 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 13-7, the receiver counts 170 RT cycles at the point 170 163 – × 100 = 4.12% ------------------------- - 170 Freescale Semiconductor ...
Page 133
... If they are not the same, software can set the RWU bit and put the receiver back into the standby state. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor STOP IDLE OR NEXT CHARACTER ...
Page 134
... Noise flag (NF) — The NF bit is set when the ESCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate ESCI error interrupt requests. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 134 NOTE Freescale Semiconductor ...
Page 135
... ESCI Transmit Data (TxD) The TxD pin is the serial data output from the ESCI transmitter. When the ESCI is enabled, the TxD pin becomes an output. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Low-Power Modes Figure 13-1 for the port pins ...
Page 136
... ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode Loop mode enabled 0 = Normal operation enabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 136 TXINV M WAKE Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 137
... This read/write bit enables the ESCI parity function (see function inserts a parity bit in the MSB position (see 1 = Parity function enabled 0 = Parity function disabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Table 13-4. Character Format Selection Character Format Start Bits ...
Page 138
... This read/write bit enables the SCRF bit to generate ESCI receiver interrupt requests. Setting the SCRIE bit in SCC2 enables the SCRF bit to generate interrupt requests SCRF enabled to generate interrupt 0 = SCRF not enabled to generate interrupt MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 138 NOTE TCIE SCRIE ILIE Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 139
... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE NOTE NOTE Registers ...
Page 140
... This read/write bit enables ESCI receiver interrupt requests generated by the parity error bit, PE ESCI error interrupt requests from PE bit enabled 0 = ESCI error interrupt requests from PE bit disabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 140 ORIE Reserved 2 1 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...
Page 141
... ESCI receiver interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...
Page 142
... BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-13. Flag Clearing Sequence BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...
Page 143
... Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 144
... The break symbol length must be verified in software in any case, but the LINR bit serves as a filter, preventing false detections of break characters that are really 0x00 data characters. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 144 Unaffected by reset NOTE NOTE LINR SCP1 SCP0 Bit Bit 0 SCR2 SCR1 SCR0 Freescale Semiconductor ...
Page 145
... There are two prescalers available to adjust the baud rate — one in the ESCI baud rate register and one in the ESCI prescaler register. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 13-5. ESCI LIN Control Bits M Functionality ...
Page 146
... ESCI baud rates that can be generated with a 4.9152-MHz bus frequency. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 146 PDS1 PDS0 PSSB4 PSSB3 NOTE Prescaler Divisor (PD) Bypass this prescaler Frequency of the SCI clock source 64 x BPD (PD + PDFA Bit 0 PSSB2 PSSB1 PSSB0 Table 13-8. Table 13-9. Freescale Semiconductor ...
Page 147
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/ ...
Page 148
... Freescale Semiconductor ...
Page 149
... Bit time measurement has finished 0 = Bit time measurement not yet finished ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running Arbiter counter running 0 = Arbiter counter stopped MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor AFIN AM0 ...
Page 150
... The counter will be stopped on the next rising edge of RxD. This mode is used to measure the length of a received break. RXD Figure 13-20. Bit Time Measurement with ACLK = 0 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 150 ARD6 ARD5 ARD4 ARD3 MEASURED TIME 2 1 Bit 0 ARD2 ARD1 ARD0 Figure 13-21 RxD on Freescale Semiconductor ...
Page 151
... If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor MEASURED TIME MEASURED TIME ESCI Arbiter ...
Page 152
... Enhanced Serial Communications Interface (ESCI) Module MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 152 Freescale Semiconductor ...
Page 153
... The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, BUSCLKX2, as shown in MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure Table 14-1. Signal Name Conventions Description Buffered clock from the internal XTAL oscillator circuit ...
Page 154
... BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE BUS CLOCK GENERATORS Freescale Semiconductor ...
Page 155
... RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS PC MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 14.7.2 Stop Mode. 14.5 SIM Counter), but an external reset does not. Each of shows the relative timing. The RST pin function is only available VECT H VECT L Figure 14-3 ...
Page 156
... RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 14-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 14-5. Sources of Internal Reset Table 14-2. Reset Recovery Timing Actual Number of Cycles 4163 (4096 + VECTOR HIGH 67 ( Freescale Semiconductor ...
Page 157
... The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 4096 32 32 ...
Page 158
... SSREC cleared in the configuration register 1 (CONFIG1). MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 158 Figure 2-1. Memory Map voltage falls to the LVI trip voltage V DD rises above V . Sixty-four BUSCLKX4 DD TRIPR for memory ranges. . The LVI TRIPF Freescale Semiconductor ...
Page 159
... H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 14.7.2 Stop Mode 14.4.2 Active Resets from Internal Sources shows interrupt recovery timing. ...
Page 160
... BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO Figure 14-7. Interrupt Processing STACK CPU REGISTERS SET I BIT EXECUTE INSTRUCTION Freescale Semiconductor ...
Page 161
... DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 14-10 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor SP – – – – – 1[7:0] PC – 1[15: Figure 14-8 Interrupt Entry SP – – – 1 ...
Page 162
... IF11 $FFE6–$FFE7 IF12 $FFE4–$FFE5 IF13 $FFE2–$FFE3 IF14 $FFE0–$FFE1 IF15 $FFDE–$FFDF IF16 $FFDC–$FFDD IF17 $FFDA–$FFDB IF18 $FFD8–$FFD9 IF19 $FFD6–$FFD7 Freescale Semiconductor ...
Page 163
... These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present 14.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor IF5 ...
Page 164
... Some modules can be programmed to be active in wait mode. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 164 Support.) The SIM puts the CPU into the break WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-14. Wait Mode Entry Timing Figure 14-14 shows SAME SAME SAME Freescale Semiconductor ...
Page 165
... External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor show the timing for wait recovery. $6E0B $6E0C $00FF ...
Page 166
... STOP RECOVERY PERIOD STOP + 2 STOP + 2 STOP +1 Table 14-4 shows the mapping of these registers. Table 14-4. SIM Registers Register BSR SRSR BFCR shows stop mode entry timing and SAME SAME SAME SP SP – – – 3 Access Mode User User User Freescale Semiconductor ...
Page 167
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ V TST 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor PIN COP ILOP ...
Page 168
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 168 Bit Freescale Semiconductor ...
Page 169
... MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. The following paragraphs describe the operation of the SPI module. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-1 for port location 169 ...
Page 170
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 171
... CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER interrupt REQUEST RECEIVER/ERROR interrupt REQUEST MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR MODFEN ...
Page 172
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 172 NOTE Figure 15-3. MISO MISO MOSI MOSI SPSCK SPSCK Register.) Through the SPSCK pin, the baud rate generator of the 15.8.1 SPI SLAVE MCU SHIFT REGISTER 15.3.6.2 Mode Fault Error. Freescale Semiconductor ...
Page 173
... The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor 15.3.3 Transmission Formats. ...
Page 174
... MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 174 15.3.6.2 Mode Fault MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 BYTE 1 BYTE 2 Figure 15-5. CPHA/SS Timing Error.) When CPHA = 0, the first BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB BYTE 3 Freescale Semiconductor ...
Page 175
... This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 176
... SPSCK = BUS CLOCK ÷ 2; EARLIEST 2 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 32; EARLIEST 32 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...
Page 177
... For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 178
... SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 178 Figure 15-4 and Figure 15-6 overflow occurs, all data Figure Figure 15-9 15-11 not possible shows how it is Freescale Semiconductor ...
Page 179
... READ BYTE 1 IN SPDR, CLEARING SPRF BIT. 4 READ SPSCR AGAIN TO CHECK OVRF BIT. Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-10 illustrates this process. Generally, to avoid this second BYTE 2 BYTE 3 4 ...
Page 180
... MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur because a transmission was never begun. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 180 Figure NOTE 15.3.3 Transmission Formats. NOTE 15-11 not possible Freescale Semiconductor ...
Page 181
... SPE. See ERRIE MODF OVRF Figure 15-11. SPI Interrupt Request Generation MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Table 15-1. SPI Interrupts Request SPI transmitter interrupt request (SPTIE = 1, SPE = 1) SPI receiver interrupt request (SPRIE = 1) ...
Page 182
... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 182 15.4 Interrupts. sheet. Freescale Semiconductor ...
Page 183
... I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of SS from creating a MODF error. See MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-1 for the port pins Figure 15-12 ...
Page 184
... Mode Fault Table 15-2. SPI Configuration SPI Configuration Not enabled General-purpose I/O; SS ignored by SPI Slave Master without MODF General-purpose I/O; SS ignored by SPI Master with MODF BYTE 3 Error.) For the state Function of SS Pin Input-only to SPI Input-only to SPI Freescale Semiconductor ...
Page 185
... This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register SPTE interrupt requests enabled 0 = SPTE interrupt requests disabled MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 186
... MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR pin at inappropriate logic level pin at appropriate logic level MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 186 OVRF MODF SPTE Bit 0 MODFEN SPR1 SPR0 Freescale Semiconductor ...
Page 187
... In master mode, these read/write bits select one of four baud rates as shown in SPR0 have no effect in slave mode. Table 15-3. SPI Master Baud Rate Selection SPR1 and SPR0 Use this formula to calculate the SPI baud rate: MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Baud Rate Divisor (BD ...
Page 188
... R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register because the register read is not the same as the register written. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 188 Figure Unaffected by reset Figure 15-15. SPI Data Register (SPDR) NOTE 15- Bit Freescale Semiconductor ...
Page 189
... T1MODH:T1MODL, control the modulo value of the counter. Software can read the counter value, T1CNTH:T1CNTL, at any time without affecting the counting sequence. The four TIM1 channels are programmable independently as input capture or output compare channels. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 16-1 Figure 16-1 for ...
Page 190
... Introduction) CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE LOW-VOLTAGE INHIBIT 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MONITOR ROM Freescale Semiconductor ...
Page 191
... CHANNEL 1 16-BIT COMPARATOR T1CH1H:T1CH1L 16-BIT LATCH CHANNEL 2 16-BIT COMPARATOR T1CH2H:T1CH2L 16-BIT LATCH CHANNEL 3 16-BIT COMPARATOR T1CH3H:T1CH3L 16-BIT LATCH MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F ...
Page 192
... Setting the MS0B bit in TIM1 channel 0 status and control register (T1SC0) links channel 0 and channel 1. The output compare value in the TIM1 channel 0 registers initially controls the output on the T1CH0 pin. Writing to the TIM1 channel 1 registers enables the TIM1 channel 1 registers to synchronously control the MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 192 16.3.3 Freescale Semiconductor ...
Page 193
... TIM1 to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1). OVERFLOW POLARITY = 1 (ELSxA = 0) T1CHx POLARITY = 0 T1CHx (ELSxA = 1) Figure 16-3. PWM Period and Pulse Width MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE OVERFLOW PERIOD PULSE WIDTH OUTPUT OUTPUT COMPARE COMPARE ...
Page 194
... PWM period. At each subsequent overflow, the TIM1 channel registers ( that control the pulse width are the ones written to last. T1SC0 controls and monitors the buffered PWM MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 194 16.8.1 TIM1 Status and Control NOTE Register. 16.3.4 Pulse Width Freescale Semiconductor ...
Page 195
... PWM signal generation when changing the PWM pulse width to a new, much larger value the TIM1 status control register (T1SC), clear the TIM1 stop bit, TSTOP. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Table 16-2. ...
Page 196
... The TIM1 module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. TIM1 operation resumes after an external interrupt. If stop mode is exited by reset, the TIM1 is reset. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 196 Registers. Freescale Semiconductor ...
Page 197
... Enables TIM1 overflow interrupts • Flags TIM1 overflows • Stops the counter • Resets the counter • Prescales the counter clock MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor TIM1 During Break Interrupts sheet. Figure 16-1 for the port pins 197 ...
Page 198
... Prescaler and counter cleared effect Setting the TSTOP and TRST bits simultaneously stops the counter at a value of $0000. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 198 TOIE TSTOP TRST NOTE NOTE 2 1 Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...
Page 199
... Figure 16-5. TIM1 Counter High Register (T1CNTH) Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 16-6. TIM1 Counter Low Register (T1CNTL) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 Freescale Semiconductor Table 16-1. Prescaler Selection PS1 PS0 TIM1 Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ ...
Page 200
... Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5 200 Bit14 Bit13 Bit12 Bit11 Bit6 Bit5 Bit4 Bit3 NOTE 2 1 Bit 0 Bit10 Bit9 Bit8 Bit 0 Bit2 Bit1 Bit0 Freescale Semiconductor ...