MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet - Page 145

IC MCU 8BIT 16K FLASH 28-SOIC

MC908QC16CDZE

Manufacturer Part Number
MC908QC16CDZE
Description
IC MCU 8BIT 16K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC908QC16CDZE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08QC
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
ESCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
26
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
For Use With
DEMO908QC16 - BOARD DEMO FOR MC908QC16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
SCR2–SCR0 — ESCI Baud Rate Select Bits
13.8.8 ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for
both the receiver and the transmitter.
Freescale Semiconductor
These read/write bits select the baud rate register prescaler divisor as shown in
These read/write bits select the ESCI baud rate divisor as shown in
SCR2–SCR0.
There are two prescalers available to adjust the baud rate — one in the
ESCI baud rate register and one in the ESCI prescaler register.
LINT
0
0
0
1
1
1
1
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
LINR
0
1
1
0
0
1
1
SCP[1:0]
SCR[2:1:0]
0 0
0 1
1 0
1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 13-6. ESCI Baud Rate Prescaling
Table 13-7. ESCI Baud Rate Selection
Table 13-5. ESCI LIN Control Bits
M
X
0
1
0
1
0
1
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
NOTE
Prescaler Divisor (BPD)
Baud Rate Divisor (BD)
Baud Rate Register
Functionality
13
1
3
4
128
16
32
64
1
2
4
8
Table
13-7. Reset clears
Table
13-6.
Registers
145

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