MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet - Page 179

• Manufacturer Part Number: MC908QC16CDZE
• Description: IC MCU 8BIT 16K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QC16CDZE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08QC
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• For Use With: DEMO908QC16 - BOARD DEMO FOR MC908QC16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR
are read.
In this case, an overflow can be missed easily. Because no more SPRF interrupts can be generated until
this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of
the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit.
SPSCR read, enable OVRF by setting the ERRIE bit.
Freescale Semiconductor
1
2
3
4
BYTE 1 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
READ BYTE 1 IN SPDR,
CLEARING SPRF BIT.
READ SPSCR AGAIN TO CHECK OVRF BIT.
SPSCR
OVRF
READ
READ
SPDR
SPRF
SPI RECEIVE
COMPLETE
Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
SPSCR
1
2
3
4
BYTE 1
OVRF
READ
READ
SPDR
SPRF
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
BYTE 1 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
READ BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
1
BYTE 1
2
Figure 15-9. Missed Read of Overflow Condition
1
2
3
5
6
7
8
Figure 15-10
3
BYTE 2 SETS SPRF BIT.
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
READ BYTE 2 IN SPDR, CLEARING SPRF BIT.
BYTE 2
4
BYTE 2
4
5
illustrates this process. Generally, to avoid this second
BYTE 3
BYTE 3
5
5
6
7
8
6
6
READ SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
READ BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
7
7
8
9
BYTE 4
BYTE 4
10
11
12
13
14
10
9
11
8
READ SPSCR AGAIN TO CHECK OVRF BIT.
READ BYTE 2 SPDR, CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
READ SPSCR.
READ BYTE 4 IN SPDR, CLEARING SPRF BIT.
READ SPSCR AGAIN TO CHECK OVRF BIT.
12
13
Functional Description
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