MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet - Page 65

• Manufacturer Part Number: MC908QC16CDZE
• Description: IC MCU 8BIT 16K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QC16CDZE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08QC
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• For Use With: DEMO908QC16 - BOARD DEMO FOR MC908QC16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1
(CONFIG1). See
5.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
5.5 Interrupts
The COP does not generate CPU interrupt requests.
5.6 Monitor Mode
The COP is disabled in monitor mode when V
5.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
5.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter.
5.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
5.8 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
Freescale Semiconductor
Reset:
Read:
Write:
Chapter 4 Configuration Registers (CONFIG1 and
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Bit 7
Figure 5-2. COP Control Register (COPCTL)
6
5
LOW BYTE OF RESET VECTOR
TST
CLEAR COP COUNTER
Unaffected by reset
is present on the IRQ pin.
4
3
2
CONFIG2).
1
COP Control Register
Bit 0
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