MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet - Page 110

• Manufacturer Part Number: MC908QC16CDZE
• Description: IC MCU 8BIT 16K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QC16CDZE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08QC
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• For Use With: DEMO908QC16 - BOARD DEMO FOR MC908QC16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Input/Output Ports (PORTS)
11.4 Port B
Port B is an 8-bit general purpose I/O port. Each port B pin can be configured to have an internal pullup
when used as an input port pin.
11.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
PTB[7:0] — Port B Data Bits
11.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
110
Table 11-1
1. X = don’t care
2. I/O pin pulled to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
PTAPUE
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
Bit
X
1
0
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
summarizes the operation of the port A pins.
Reset:
Reset:
Read:
Write:
Read:
Write:
DDRA
Bit
0
0
1
DD
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
DDRB7
by internal pullup.
PTB7
Bit 7
Bit 7
0
PTA
X
Bit
X
X
(1)
Figure 11-6. Data Direction Register B (DDRB)
DDRB6
PTB6
Figure 11-5. Port B Data Register (PTB)
6
6
0
Input, V
Input, Hi-Z
Table 11-1. Port A Pin Functions
I/O Pin
Output
Mode
DDRB5
DD
PTB5
5
5
0
(2)
(4)
DDRB4
Unaffected by reset
PTB4
4
4
0
Accesses to DDRA
DDRA5–DDRA0
DDRA5–DDRA0
DDRA5–DDRA0
Read/Write
DDRB3
PTB3
3
3
0
DDRB2
PTB2
2
2
0
PTA5–PTA0
DDRB1
PTB1
Read
1
1
0
Pin
Pin
Accesses to PTA
Freescale Semiconductor
DDRB0
PTB0
Bit 0
Bit 0
0
PTA5–PTA0
PTA5–PTA0
PTA5–PTA0
Write
(3)
(3)
(5)