MC908QC16CDZE Freescale Semiconductor, MC908QC16CDZE Datasheet - Page 201

• Manufacturer Part Number: MC908QC16CDZE
• Description: IC MCU 8BIT 16K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QC16CDZE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08QC
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: ESCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• For Use With: DEMO908QC16 - BOARD DEMO FOR MC908QC16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
Freescale Semiconductor
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the T1SCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Writing a 1 to CHxF has no effect.
This read/write bit enables TIM1 interrupt service requests on channel x.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 16-10. TIM1 Channel 1 Status and Control Register (T1SC1)
Figure 16-11. TIM1 Channel 2 Status and Control Register (T1SC2)
Figure 16-12. TIM1 Channel 3 Status and Control Register (T1SC3)
Figure 16-9. TIM1 Channel 0 Status and Control Register (T1SC0)
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
CH0F
CH1F
CH2F
CH3F
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
CH0IE
CH1IE
CH2IE
CH3IE
6
0
6
0
6
0
6
0
MS0B
MS2B
5
0
5
0
0
5
0
5
0
0
MS0A
MS1A
MS2A
MS3A
4
0
4
0
4
0
4
0
ELS0B
ELS1B
ELS2B
ELS3B
3
0
3
0
3
0
3
0
ELS0A
ELS1A
ELS2A
ELS3A
2
0
2
0
2
0
2
0
TOV0
TOV1
TOV2
TOV3
1
0
1
0
1
0
1
0
CH0MAX
CH1MAX
CH2MAX
CH3MAX
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
Registers
201