HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 137

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
7.4.3
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
2. If interrupt exception handling starts before the vector address is written or during
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
register (EBR1). To erase multiple blocks, each block must be erased in turn.
overflow cycle of approximately 19.8 ms is allowed.
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
algorithm, with the result that normal operation cannot be assured.
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
carried out.
Erase/Erase-Verify
Interrupt Handling when Programming/Erasing Flash Memory
Rev. 6.00 Mar. 24, 2006 Page 107 of 412
REJ09B0142-0600
Section 7 ROM