HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 187

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.6
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
3. If compare matches A and B occur simultaneously, any conflict between the output selections
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
11.12 shows the timing.
for compare match A and compare match B is resolved by the following priority: toggle
output > output 1 > output 0.
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown
in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
Usage Notes
Figure 11.11 Contention between TCNTV Write and Clear
Address
Internal
write signal
Counter clear
signal
TCNTV
TCNTV write cycle by CPU
T
1
TCNTV address
N
T
2
T
Rev. 6.00 Mar. 24, 2006 Page 157 of 412
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Section 11 Timer V
REJ09B0142-0600