HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 85

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2.3
IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Bit
7
6
5
4
3
2
1
0
Interrupt Enable Register 1 (IENR1)
Bit Name
IENDT
IENTA
IENWP

IEN3
IEN2
IEN1
IEN0
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
Description
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
Timer A Interrupt Enable
When this bit is set to 1, timer A overflow interrupt
requests are enabled.
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
Reserved
This bit is always read as 1.
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.
IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
Rev. 6.00 Mar. 24, 2006 Page 55 of 412
Section 3 Exception Handling
REJ09B0142-0600