HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 274

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 I
Rev. 6.00 Mar. 24, 2006 Page 244 of 412
REJ09B0142-0600
Bit
1
Bit Name
IRIC
2
C Bus Interface (IIC)
Initial
Value
0
R/W
R/W
Description
I
Also see table 15.4.
[Setting conditions]
In master mode with I
•
•
•
•
•
I
•
•
•
•
Clocked synchronous serial format
•
•
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
2
2
C Bus Interface Interrupt Request Flag
C bus format slave mode
When a start condition is detected in the bus line
state after a start condition is issued
When a wait is inserted between the data and
acknowledge bit when WAIT = 1
At the rising edge of the ninth transfer/receive clock,
and at the falling edge of the eighth transfer/receive
clock when a wait is inseted
When a slave address is received after bus
arbitration is lost (when the AL flag is set to1)
When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (FS = 0 and when the TDRE or RDRF flag
is set to 1)
When the general call address is detected (when
the ADZ flag is set to 1) and at the end of data
transfer up to the subsequent retransmission start
condition or stop condition detection (when the
TDRE or RDRF flag is set to 1)
When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
When a stop condition is detected (when the STOP
or ESTP flag is set to 1)
At the end of data transfer (when the TDRE or
RDRF flag is set to 1)
When a start condition is detected with serial format
selected
2
C bus format