HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 302

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 I
• Notes on TRS Bit Setting and ICDR Register Access
Rev. 6.00 Mar. 24, 2006 Page 272 of 412
REJ09B0142-0600
SDA
SCL
TRS bit
RDRF bit
ICDRS data full
 Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are
satisfied.
Master mode:
Figure 15.19 shows the notes on ICDR reading (TRS = 1) in master mode.
(a) When previously received 2-byte data remains in ICDR unread (ICDRS are full).
(b) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(c) Sets to receive mode (TRS = 0), after transmitting the first frame of issued start
Slave mode:
Figure 15.20 shows the notes on ICDR writing (TRS = 0) in slave mode.
(a) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by
(b) Address match with the first frame, receive 1 by R/W bit, and switches to transmit
When these conditions are satisfied, the low fixation of the SCL pins is cancelled without
ICDR register access after the first frame is transferred.
Figure 15.19 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
condition by master mode.
slave mode (TDRE = 0 state).
mode (TRS = 1).
2
C Bus Interface (IIC)
Detection of 9th clock rise
(TRS = 1)
8
Stop condition
A
9
ICDR read
Start condition
1
2
3
4
Address
5
(a) ICDRS data full
6
(b) RDRF = 0
7
Along with ICDRS
8
Cancel condition of SCL =
Low fixation is set.
A
9
TRS = 0 setting
1
ICDRR transfer
Data
(c) TRS = 0
2
3