HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 297

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. The I
Table 15.6 Permissible SCL Rise Time (t
6. The I
IICX
0
1
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 15.6.
and 300 ns. The I
shown in table 15.5. However, because of the rise and fall times, the I
specifications may not be satisfied at the maximum transfer rate. Table 15.7 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times. The values in the above table will vary depending on the settings of the
IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to
achieve the maximum transfer rate; therefore, whether or not the I
specifications are met must be determined in accordance with the actual setting conditions.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
BUFO
SCLLO
t
Indication
7.5t
17.5t
cyc
fails to meet the I
in high-speed mode and t
2
2
C bus interface specification for the SCL rise time t
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
Normal mode
High-speed mode 300 ns
Normal mode
High-speed mode 300 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
in standard mode fail to satisfy the I
2
I
Specification
(Max.)
1000 ns
1000 ns
C bus interface monitors the SCL line and synchronizes
2
C Bus
sr
) Values
sr
(the time for SCL to go from low to V
Sr
/t
2
C bus interface, the high period of SCL is
Sf
. Possible solutions that should be
φ =
5 MHz
1000 ns
300 ns
1000 ns
300 ns
sr
Rev. 6.00 Mar. 24, 2006 Page 267 of 412
Time Indication
is under 1000 ns (300 ns for high-
φ =
8 MHz
937 ns
300 ns
1000 ns
300 ns
Section 15 I
2
C bus interface
2
C bus.
2
C bus interface
2
C bus interface
φ =
10 MHz
750 ns
300 ns
1000 ns
300 ns
2
C Bus Interface (IIC)
REJ09B0142-0600
Scyc
and t
IH
) exceeds
φ = 16
MHz
468 ns
300 ns
1000 ns
300 ns
cyc
2
C
, as