HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 277

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
2
1
0
Bit Name
AAS
ADZ
ACKB
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Slave Address Recognition Flag
[Setting condition]
When the slave address or general call address is
detected in slave receive mode and FS = 0.
[Clearing conditions]
•
•
•
General Call Address Recognition Flag
This bit is valid in I
[Setting condition]
When the general call address is detected in slave
receive mode and FSX = 0 or FS = 0.
[Clearing conditions]
•
•
•
Acknowledge Bit
In transmit mode, the acknowledge data that are
returned by the receive device is loaded. In receive
mode, the acknowledge data originally specified to this
bit is sent to the transmit device, after receiving data.
When this bit is read, the loaded value (return value
from the receive device) is read at transmission and the
specified value is read at reception.
When ICDR data is written (transmit mode) or read
(receive mode)
When 0 is written in AAS after reading AAS = 1
In master mode
When ICDR data is written (transmit mode) or read
(receive mode)
When 0 is written in ADZ after reading ADZ = 1
In master mode
2
Rev. 6.00 Mar. 24, 2006 Page 247 of 412
C bus format slave receive mode.
Section 15 I
2
C Bus Interface (IIC)
REJ09B0142-0600