HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 233

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.7
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit
7
6
5
4
Serial Status Register (SSR)
Bit Name
TDRE
RDRF
OER
FER
Initial
Value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
•
•
Overrun Error
[Setting condition]
When an overrun error occurs in reception
[Clearing condition]
When 0 is written to OER after reading OER = 1
Framing Error
[Setting condition]
When a framing error occurs in reception
[Clearing condition]
When 0 is written to FER after reading FER = 1
When the TE bit in SCR3 is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When the transmit data is written to TDR
When 0 is written to RDRF after reading RDRF =
1
When data is read from RDR
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 203 of 412
REJ09B0142-0600