HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 282

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 I
9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit
12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low
Rev. 6.00 Mar. 24, 2006 Page 252 of 412
REJ09B0142-0600
(master output)
(master output)
(slave output)
User processing
Note: * Data write timing in ICDR
ICDR writing
prohibited
cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in the step
[6]. Transmission of the next frame is performed in synchronization with the internal clock.
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
is 0). When there is data to be transmitted, go to the step [9] to continue next transmission.
When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to
end transmission.
to high when SCL is high, and generates the stop condition.
SDA
SCL
SDA
ICDR
IRTR
IRIC
Start condition generation
*
2
C Bus Interface (IIC)
[4] Write BBSY = 1
Figure 15.5 Master Transmit Mode Operation Timing Example
and SCP = 0
(start condition
issuance)
[5]
Normal
operation
[6] ICDR write
Bit 7
1
Address + R/W
Bit 6
2
(MLS = WAIT = 0)
Bit 5
[6] IRIC clearance
3
Slave address
Slave address
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
R/W
8
[7]
9
A
[9] ICDR write
[9] IRIC clearance
Bit 7
Data 1
1
Data 1
Bit 6
2