HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 257

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.2
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
14.18 shows an example of SCI3 operation for multiprocessor format reception.
Multiprocessor Serial Data Reception
Yes
No
No
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
Read OER and FER flags in SSR
Read OER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Set MPIE bit in SCR3 to 1
Clear RE bit in SCR3 to 0
Read RDRF flag in SSR
Read RDRF flag in SSR
All data received?
This station's ID?
Start reception
FER+OER = 1
FER+OER = 1
RDRF = 1
RDRF = 1
<End>
Yes
Yes
Yes
No
No
No
[A]
Yes
No
Yes
[3]
[1]
[2]
Error processing
Section 14 Serial Communication Interface 3 (SCI3)
(Continued on
[4]
[5]
next page)
[1] Set the MPIE bit in SCR3 to 1.
[2] Read OER and FER in SSR to check for
[3] Read SSR and check that the RDRF flag
[4] Read SSR and check that the RDRF flag
[5] If a receive error occurs, read the OER
errors. Receive error processing is
performed in cases where a receive error
occurs.
is set to 1, then read the receive data in
RDR and compare it with this station’s
ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
is set to 1, then read the data in RDR.
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the OER
and FER flags are all cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Rev. 6.00 Mar. 24, 2006 Page 227 of 412
REJ09B0142-0600