HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 311

IC H8/3664 MCU FLASH 32K 64LQFP

HD64F3664FPV

Manufacturer Part Number
HD64F3664FPV
Description
IC H8/3664 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3664FPV

Core Size
16-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300H
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
No. Of I/o's
29
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
16.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
16.4.1
In single mode, A/D conversion is performed once for the analog input on the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
16.4.2
In scan mode, A/D conversion is performed sequentially for the analog input on the specified
channels (four channels maximum) as follows:
1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the
external trigger input.
register to the channel.
this time, an ADI interrupt request is generated.
bit is automatically cleared to 0 and the A/D converter enters the wait state.
the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Operation
Single Mode
Scan Mode
Rev. 6.00 Mar. 24, 2006 Page 281 of 412
Section 16 A/D Converter
REJ09B0142-0600

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