HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 266

IC H8/3664 MCU FLASH 32K 64LQFP

HD64F3664FPV

Manufacturer Part Number
HD64F3664FPV
Description
IC H8/3664 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3664FPV

Core Size
16-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300H
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
No. Of I/o's
29
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Section 15 I
15.3
The I
one address, and registers that can be accessed depend on the ICE bit in ICCR. When ICE = 0.
SAR and SARX can be accessed. When ICE = 1, ICMR and ICDR can be accessed.
• I
• I
• I
• I
• Slave address register (SAR)
• Second slave address register (SARX)
• Timer serial control register (TSCR)
15.3.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit
buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When
RDRF is 1, it shows that the valid receive data is stored in the receive buffer.
If I
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If I
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR can be written and read only when the ICE bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
Rev. 6.00 Mar. 24, 2006 Page 236 of 412
REJ09B0142-0600
2
C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
2
2
2
2
C bus control register (ICCR)
C bus status register (ICSR)
C bus data register (ICDR)
C bus mode register (ICMR)
2
C bus interface has the following registers. ICDR, SARX, ICMR, and SAR are allocated to
Register Descriptions
I
2
2
C Bus Data Register (ICDR)
C Bus Interface (IIC)
2
C is in receive mode and no previous data remains in ICDRR (the RDRF

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