HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 139

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to
H'00, erase protection is set for all blocks.
7.5.3
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
(including vector read and instruction fetch)
Program/Erase Protection
Hardware Protection
Software Protection
Error Protection
Rev. 6.00 Mar. 24, 2006 Page 109 of 412
REJ09B0142-0600
Section 7 ROM