HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 312

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 16 A/D Converter
16.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
Rev. 6.00 Mar. 24, 2006 Page 282 of 412
REJ09B0142-0600
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total conversion
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
(2):
t
t
t
D
SPL
CONV
:
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay
Input sampling time
Figure 16.2 A/D Conversion Timing
(1)
(2)
D
) has passed after the ADST bit is set to 1, then
D
and the input sampling time. The