HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 241

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.2
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
SCI3 Initialization
and MPIE bits. For transmit (TE=1),
SCR3 to 1, and set RIE, TIE, TEIE,
Clear TE and RE bits in SCR3 to 0
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
also set the TxD bit in PMR1.
<Initialization completion>
1-bit interval elapsed?
Set TE and RE bits in
Set value in BRR
Start initialization
Figure 14.4 Sample SCI3 Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
[1] Set the clock selection in SCR3.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
[4] Wait at least one bit interval, then set
Section 14 Serial Communication Interface 3 (SCI3)
Be sure to clear bits RIE, TIE, TEIE,
and MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in
clocked synchronous mode, clock is
output immediately after CKE1, CKE0,
and RE are set to 1.
rate to BRR. Not necessary if an
external clock is used.
the TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be
used. For transmission, set the TXD bit
in PMR1 to 1 to enable the TXD output
pin to be used. Also set the RIE, TIE,
TEIE, and MPIE bits, depending on
whether interrupts are required. In
asynchronous mode, the bits are
marked at transmission and idled at
reception to wait for the start bit.
Rev. 6.00 Mar. 24, 2006 Page 211 of 412
REJ09B0142-0600