HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 92

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 3 Exception Handling
3.4.4
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2
Note:
Rev. 6.00 Mar. 24, 2006 Page 62 of 412
REJ09B0142-0600
Item
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
Instruction fetch
Internal processing
*
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
[Legend]
PC H :
PC L :
CCR:
SP:
Notes:
Interrupt Response Time
Not including EEPMOV instruction.
Interrupt Wait States
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
2.
3. Ignored when returning from the interrupt handling routine.
1.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Prior to start of interrupt
Figure 3.2 Stack Status after Exception Handling
exception handling
Stack area
saved to stack
PC and CCR
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
States
1 to 23
4
2
4
4
exception handling
CCR
CCR
PCH
PCL
*3
Even address
Total
15 to 37