HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 269

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15.2 Communication Format
15.3.4
The I
accessed when the ICE bit in ICCR is 1.
SAR
FS
0
0
1
1
Bit
7
6
5
4
3
2
C bus mode register (ICMR) sets the transfer format and transfer rate. It can only be
I
2
Bit Name
MLS
WAIT
CKS2
CKS1
CKS0
C Bus Mode Register (ICMR)
SARX
FSX
0
1
0
1
Initial
Value
0
0
0
0
0
I
SAR and SARX are used as the slave addresses with the I
format.
Only SAR is used as the slave address with the I
Only SARX is used as the slave address with the I
Clock synchronous serial format (SAR and SARX are invalid)
2
C Transfer Format
R/W
R/W
R/W
R/W
R/W
R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
format.
When WAIT is set to 1, after the fall of the clock for the
final data bit, the IRIC flag is set to 1 in ICCR, and a
wait state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0,
data and acknowledge bits are transferred
consecutively with no wait inserted. The IRIC flag in
ICCR is set to 1 on completion of the acknowledge bit
transfer, regardless of the WAIT setting.
Serial Clock Select 2 to 0
This bit is valid only in master mode.
These bits select the required transfer rate, together
with the IICX bit in TSCR. Refer table 15.3.
Rev. 6.00 Mar. 24, 2006 Page 239 of 412
Section 15 I
2
C bus format is used.
2
C bus format.
2
C bus format.
2
C Bus Interface (IIC)
REJ09B0142-0600
2
C bus
2
C bus