HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 195

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Note:
12.3.3
TIERW controls the timer W interrupt request.
Bit
0
Bit
7
6
5
4
3
2
1
0
*
Don't care.
Timer Interrupt Enable Register W (TIERW)
Bit Name
TOA
Bit Name
OVIE



IMIED
IMIEC
IMIEB
IMIEA
The change of the setting is immediately reflected in the output value.
0
0
0
0
0
0
Initial
Value
Initial
Value
1
1
1
R/W
R/W
R/W
R/W



R/W
R/W
R/W
R/W
Description
Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
Description
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by
OVF flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
Rev. 6.00 Mar. 24, 2006 Page 165 of 412
Section 12 Timer W
REJ09B0142-0600