DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 137
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.2.3
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.4
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC * and
DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read
or written to. Register reading and writing is enabled when module stop mode is exited.
Note: * The DMAC is not supported in the H8S/2321.
RES
Address bus
RD
HWR, LWR
D
(1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
(2), (4) Start address (contents of reset exception vector address)
(5)
(6)
Note: * 3 program wait states are inserted.
15
Interrupts after Reset
State of On-Chip Supporting Modules after Reset Release
to D
φ
0
Start address ((5) = (2), (4))
First program instruction
Figure 4.2 Reset Sequence (Mode 4)
*
(1)
Vector fetch
(2)
Rev.6.00 Sep. 27, 2007 Page 105 of 1268
High
*
(3)
Internal
processing
(4)
Section 4 Exception Handling
Prefetch of first
program instruction
(5)
*
REJ09B0220-0600
(6)
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