DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 707
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 707 of 1304
- Download datasheet (8Mb)
15.2.3
Note: * The DMAC is not supported in the H8S/2321.
The function of bits 7, 6, 3, and 2 of SMR changes in smart card interface mode.
Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set
to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced,
and clock output control mode addition is performed. The contents of the clock output control
mode addition are specified by bits 1 and 0 of the serial control register (SCR).
Bit 7
GM
0
1
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bit
Initial value :
R/W
Serial Mode Register (SMR)
Description
Normal smart card interface mode operation
•
•
GSM mode smart card interface mode operation
•
•
:
:
TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of
start bit
Clock output on/off control only
TEND flag generation 11.0 etu after beginning of start bit
High/low fixing control possible in addition to clock output on/off control (set by
SCR)
R/W
GM
7
0
R/W
BLK
6
0
R/W
PE *
5
0
R/W
O/E
4
0
Rev.6.00 Sep. 27, 2007 Page 675 of 1268
BCP1
R/W
3
0
Section 15 Smart Card Interface
BCP0
R/W
2
0
REJ09B0220-0600
CKS1
R/W
1
0
(Initial value)
CKS0
R/W
0
0
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