DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 669
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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In serial reception, the SCI operates as described below.
[1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
[a] Parity check:
[b] Stop bit check:
[c] Status check:
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error * is detected in the error check, the operation is as shown in table 14.11.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
Section 14 Serial Communication Interface (SCI)
Rev.6.00 Sep. 27, 2007 Page 637 of 1268
REJ09B0220-0600
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