DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 470
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 470 of 1304
- Download datasheet (8Mb)
Section 9 I/O Ports
Port Function Control Register 2 (PFCR2)
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode.
Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6,
Port 5.
Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section
9.6, Port 5.
Bit 5—CS167 Enable (CS167E): Enables or disables CS
CS167E setting only when the DDR bits are cleared to 0.
Bit 5
CS167E
0
1
Bit 4—CS25 Enable (CS25E): Enables or disables CS
CS25E setting only when the DDR bits are cleared to 0.
Bit 4
CS25E
0
1
Bit 3—AS Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13,
Port F.
Bits 2 to 0—Reserved: These bits are always read as 0.
Rev.6.00 Sep. 27, 2007 Page 438 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
:
:
WAITPS
Description
CS
CS
Description
CS
CS
R/W
7
0
1
1
2
2
, CS
, CS
, CS
, CS
6
6
3
3
, and CS
, and CS
, CS
, CS
BREQOPS
R/W
6
0
4
4
, and CS
, and CS
7
7
output disabled (can be used as I/O ports)
output enabled
CS167E
R/W
5
5
5
1
output disabled (can be used as I/O ports)
output enabled
CS25E
R/W
4
1
2
, CS
1
, CS
ASOD
3
R/W
, CS
3
0
6
, and CS
4
, and CS
—
R
7
2
0
output. Change the
5
output. Change the
—
R
1
0
(Initial value)
(Initial value)
—
R
0
0
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