DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 721

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

(1) Data write
(2) Transfer from
(3) Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
I/O data
TXI
(TEND interrupt)
TDR to TSR
In case of normal transmission: TEND flag is set
In case of transmit error:
Legend:
Ds:
D0 to D7: Data bits
Dp:
DE:
Note: etu: Elementary time unit (time for transfer of 1 bit)
When GM = 0
When GM = 1
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 15.5 Relation Between Transmit Operation and Internal Registers
Start bit
Parity bit
Error signal
Figure 15.6 TEND Flag Generation Timing in Transmission
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Data 1
Data 1
Data 1
TDR
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
(shift register)
11.0 etu
Data 1
TSR
12.5 etu
Rev.6.00 Sep. 27, 2007 Page 689 of 1268
; Data remains in TDR
Data 1
Section 15 Smart Card Interface
I/O signal line output
Guard
time
DE
REJ09B0220-0600