DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 468
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 I/O Ports
9.14.2
Table 9.26 shows the port G register configuration.
Table 9.26 Port G Registers
Name
Port G data direction register
Port G data register
Port G register
Port function register 2
Notes: 1. Lower 16 bits of the address.
Port G Data Direction Register (PGDDR)
Modes 4 and 5
Modes 6 and 7
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PG4DDR bit is initialized by a reset, and in hardware standby mode, to 1 in modes 4 and 5,
and to 0 in modes 6 and 7. PGDDR retains its prior state in software standby mode. The OPE bit
in SBYCR is used to select whether the bus control output pins retain their output state or become
high-impedance when a transition is made to software standby mode.
Rev.6.00 Sep. 27, 2007 Page 436 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
Initial value :
R/W
2. Value of bits 4 to 0.
3. Initial value depends on the mode.
Register Configuration
:
:
:
Undefined Undefined Undefined
Undefined Undefined Undefined
—
—
—
7
—
—
—
6
Abbreviation
PGDDR
PGDR
PORTG
PFCR2
—
—
—
5
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
W
W
4
1
0
R/W
W
R/W
R
R/W
W
W
3
0
0
Initial Value *
H'10/H'00 *
H'00
Undefined
H'30
W
W
2
0
0
3
2
W
W
1
0
0
Address *
H'FEBF
H'FF6F
H'FF5F
H'FFAC
W
W
0
0
0
1
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