DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 429
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
Port A MOS Pull-Up Control Register (PAPCR)
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
All the bits are valid in modes 6 and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR
bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for the corresponding pin.
PAPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Open Drain Control Register (PAODR)
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA
PAODR is valid only in mode 7. Do not set PAODR bits to 1 in modes 4 to 6.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
7
to PA
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR
R/W
R/W
7
0
7
0
0
).
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
Rev.6.00 Sep. 27, 2007 Page 397 of 1268
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
Section 9 I/O Ports
REJ09B0220-0600
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
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