DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 280

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Bit 4
DTE0
0
1
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an
interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when
DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer
break interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1
transfer break interrupt.
Bit 3
DTIE1B
0
1
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0
transfer break interrupt.
Bit 1
DTIE0B
0
1
Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable
an interrupt to the CPU or DTC when transfer ends. If the DTIEA bit is set to 1 when DTE = 0,
the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt
request to the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Rev.6.00 Sep. 27, 2007 Page 248 of 1268
REJ09B0220-0600
Description
Data transfer disabled
Data transfer enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
(Initial value)
(Initial value)
(Initial value)