DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 438
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 I/O Ports
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port B Register (PORTB)
Note: * Determined by state of pins PB
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as
PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.
Rev.6.00 Sep. 27, 2007 Page 406 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
PB7DR
R/W
PB7
— *
R
7
0
7
PB6DR
R/W
PB6
— *
R
6
0
6
7
to PB
PB5DR
7
R/W
to PB
PB5
— *
R
5
0
5
0
) must always be performed on PBDR.
0
.
PB4DR
R/W
PB4
— *
R
4
0
4
PB3DR
R/W
PB3
— *
R
3
0
3
PB2DR
R/W
PB2
— *
R
2
0
2
PB1DR
R/W
PB1
— *
R
1
0
1
7
PB0DR
to PB
R/W
PB0
— *
R
0
0
0
0
).
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