HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 169

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 6.3
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so
that no transient level on the IRL/IRLS pin change is detected. In standby mode, as the peripheral
clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
The priority level of the IRL interrupt must not be lowered until the interrupt is accepted and
interrupt handling starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL/IRLS interrupt
handling.
When the interrupt level of the IRL interrupt is higher than the level set by the I3-I0 bits in the SR,
the IRL interrupt can be used to recover from standby mode (however, this only applies when the
RTC is used for 32-kHz oscillator).
I I I I R R R R L3
I I I I R R R R L L L L S S S S 3 3 3 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
L3/ / / /
L3
L3
I I I I R R R R L2
I I I I R R R R L L L L S S S S 2 2 2 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
L2/ / / /
L2
L2
I I I I R R R R L L L L 3 3 3 3 –I I I I R R R R L L L L 0 0 0 0 /I I I I R R R R L L L L S S S S 3 3 3 3 –I I I I R R R R L L L L S S S S 0 0 0 0 Pins and Interrupt Levels
I I I I R R R R L1
I I I I R R R R L L L L S S S S 1 1 1 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
L1/ / / /
L1
L1
I I I I R R R R L0
I I I I R R R R L L L L S S S S 0 0 0 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L0/ / / /
L0
L0
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rev. 5.00, 09/03, page 123 of 760
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
Interrupt Request