HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 306

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.3
10.3.1
The SH7709S supports both big endian, in which the 0 address is the most significant byte in the
byte data, and little endian, in which the 0 address is the least significant byte. Switching between
the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-
on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device’s data width and
endian. The access unit must also be matched to the device’s bus width. This also means that when
longword data is read from a byte-width device, four read operations must be performed. In the
SH7709S, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 10.7 to 10.12 show the relationship between endian, device data width, and access unit.
Table 10.7 32-Bit External Device/Big-Endian Access and Data Alignment
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Rev. 5.00, 09/03, page 260 of 760
BSC Operation
Endian/Access Size and Data Alignment
D31–D24
Data
7–0
—
—
—
Data
15–8
—
Data
31–24
D23–D16
—
Data
7–0
—
—
Data
7–0
—
Data
23–16
Data Bus
D15–D8
—
—
Data
7–0
—
—
Data
15–8
Data
15–8
D7–D0
—
—
—
Data
7–0
—
Data
7–0
Data
7–0
W W W W E E E E 3 3 3 3 ,
DQMUU
Asserted
Asserted
Asserted
W W W W E E E E 2 2 2 2 ,
DQMUL
Asserted
Asserted
Asserted
Strobe Signals
W W W W E E E E 1 1 1 1 ,
DQMLU
Asserted
Asserted
Asserted
W W W W E E E E 0 0 0 0 ,
DQMLL
Asserted
Asserted
Asserted