HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 528

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 14.23
shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure
for setting the SCI to transmit and receive serial data simultaneously is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
2. Receive error handling: If a receive error occurs, read the ORER bit in SCSSR to identify the
3. SCI status check and receive data read: Read the serial status register (SCSSR), check that
4. To continue transmitting and receiving serial data: Read the RDRF bit and SCRDR, and clear
Rev. 5.00, 09/03, page 482 of 760
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear
TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from
0 to 1.
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to
check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to
0 before the MSB (bit 7) of the current frame is transmitted.
ORER
RDRF
Serial
Serial
clock
data
RXI interrupt
request
generated
Transfer direction
Bit 7
Figure 14.22 Example of SCI Receive Operation
RXI interrupt
handler reads data
and clears RDRF
bit to 0
Bit 0
1 frame
Bit 7
RXI interrupt
request
generated
Bit 0
Bit 1
Bit 6
ERI interrupt
request generated
by overrun error
Bit 7