HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 251

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The clock pulse generator blocks function as follows:
1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the
2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal
3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the
4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock.
5. Divider 2: Divider 2 generates a clock at the operating frequency used by the peripheral clock.
6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
7. Standby Control Circuit: The standby control circuit controls the state of the clock pulse
8. Frequency Control Register: The frequency control register has control bits assigned for the
9. Standby Control Register: The standby control register has bits for controlling the power-down
input clock frequency from the CKIO pin. The multiplication rate is set by the frequency
control register. When this is done, the phase of the leading edge of the internal clock is
controlled so that it will agree with the phase of the leading edge of the CKIO pin.
oscillator or the input clock frequency from the EXTAL pin. The multiplication ratio is fixed
by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and MD2.
See table 9.3 for more information on clock operation modes.
XTAL and EXTAL pins. It operates according to the clock operating mode setting.
The operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of PLL
circuit 1, as long as it is not lower than the CKIO pin clock frequency. The division ratio is set
in the frequency control register.
The operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of PLL
circuit 1 or the CKIO pin clock frequency, as long as it is not higher than the CKIO pin clock
frequency. The division ratio is set in the frequency control register.
frequency using the MD pins and the frequency control register.
generator and other modules during clock switching and sleep/standby modes.
following functions: the frequency multiplication ratio of PLL 1, and the frequency division
ratio of the internal clock and the peripheral clock.
modes. See section 8, Power-Down Modes, for more information.
Rev. 5.00, 09/03, page 205 of 760