HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 49

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
Cache memory
Interrupt
controller (INTC)
User break
controller (UBC)
Bus state
controller (BSC)
User-debugging
Interface (UDI)
Timer (TMU)
Realtime clock
(RTC)
Features
16-kbyte cache, mixed instruction/data
256 entries, 4-way set associative, 16-byte block length
Write-back, write-through, LRU replacement algorithm
1-stage write-back buffer
Maximum 2 ways of the cache can be locked
23 external interrupt pins (NMI, IRQ5–IRQ0, PINT15 to PINT0)
On-chip peripheral interrupts: set priority levels for each module
2 break channels
Addresses, data values, type of access, and data size can all be set as break
conditions
Supports a sequential break function
Physical address space divided into six areas (area 0, areas 2 to 6), each a
maximum of 64 Mbytes, with the following features settable for each area:
Synchronous DRAM refresh function
Synchronous DRAM burst access function
Usable as either big or little endian machine
E10A emulator support
JTAG-compliant
Realtime branch address trace
1-kB on-chip RAM for fast emulation program execution
3-channel auto-reload-type 32-bit timer
Input capture function
6 types of counter input clocks can be selected
Maximum resolution: 2 MHz
Built-in clock, calendar functions, and alarm functions
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt
cycle) of 1/256 second
Bus size (8, 16, or 32 bits)
Number of wait cycles (also supports a hardware wait function)
Setting the type of space enables direct connection to SRAM,
Synchronous DRAM, and burst ROM
Supports PCMCIA interface (2 channels)
Outputs chip select signal (CS0, CS2–CS6) for corresponding area
Programmable refresh interval
Support self-refresh mode
Rev. 5.00, 09/03, page 3 of 760